This invention relates to a page mode operating memory device, and further to a data processing system having a configuration so that a plurality of data processors access a common memory device.
FIG. 8 shows a large scale-integrated DRAM (dynamic RAM) configuration, as an example of conventional semiconductor memory devices.
As shown, this LSI includes N address input terminals A, M data input/output terminals D, and four control input terminals C. A row address RA and a column address CA are externally applied to the address input terminals A via a set of address lines, in a multiplexed manner. For example, a 1M.times.1 organization DRAM of 1-megabit memory capacity has ten address input terminals A and a single data input/output terminal D. For a 20-bit address, the upper 10-bits are a row address RA and lower 10-bits are a column address CA. The row address RA and column address CA are externally applied to the ten input terminals A, respectively. On the other hand, a 1M.times.4 organization DRAM having 1-megabit memory capacity and dealing with 4-bits of data has nine address input terminals A and four data input/output terminals D. The four control input terminals C are input terminals for a row address strobe (RAS) signal, a column address strobe (CAS) signal, a write enable (WE) signal, and an output enable (OE) signal, respectively. Among the above signals that are input at the control input terminals C, the RAS signal indicates latch timing of the row address RA, and the CAS signal indicates latch timing of the column address CA. The WE signal is used to switch operations from a read operation to a write operation, and vice versa.
An internal configuration of the aforesaid memory device will be described. Reference numeral 1 represents a memory cell array which includes a plurality of unit memory cells arranged at respective points of intersection of rows and columns. Reference numeral 2 represents a row address buffer which holds a row address RA received through the address input terminals A. Reference numeral 3 represents a row decoder that decodes an output of the row address buffer 2 to select a row of data from memory cell array 1. Reference numeral 4 represents a sense and latch circuit, which reads and stores data of all columns which belong to a row selected from the memory cell array 1 by the row decoder 3, as row data for one page while at the same time amplifying them by sense amplifiers. The sense and latch circuit 4 also writes data to a row selected. Reference numeral 5 denotes a column decoder for selecting an item of data corresponding to one column designated from among the row data for one page stored in the sense and latch circuit 4. Reference numeral 6 denotes a column address buffer to store a column address CA received through the address input terminals A, and to transfer the column address CA to the column decoder 5. Reference numeral 7 represents a data input/output circuit for amplifying an item of data, selected by the column decoder 5, from the sense and latch circuit 4 under control of WE and OE signals. Data input/output circuit 7 outputs the amplified data to the data input/output terminals D as reading data or feeds data to be written to memory cell array 1 received through the data input/output terminals D, to the sense and latch circuit 4. Reference numeral 8 denotes a clock generator to generate from RAS, CAS, and WE signals various timing signals necessary for reading and writing operations to drive the row address buffer 2, the row decoder 3, the sense and latch circuit 4, the column decoder 5, and the column address buffer 6, respectively.
In accordance with the memory device, as shown in FIG. 8, having the foregoing configuration, if a RAS signal is received, an address on the address input terminals A is latched in the row address buffer 2, as a row address RA, then row data for one page selected by the row decoder 3 from the memory cell array 1 is read, and the row data thus read is latched in the sense and latch circuit 4. This operation is known as RAS access. In the case that a CAS signal is successively received, the address on the address input terminals A is latched in the column address buffer 6, as a column address CA, and an item of data, selected by the column decoder 5 from among the row data for one page that is latched in the sense and latch circuit 4, is read, then the data thus read is output through the data input/output circuit 7. This is known as CAS access.
Since the sense and latch circuit 4 always stores an entire row of data for one page, if subsequent row addresses RA are the same, that data may be read using only the CAS access where a row address RA is not received. In other words, when the range of address exceeds one page, a long cycle operation which gives both a row address RA and a column address CA individually is required. However, within the range of address for one page where the row address RA remains unchanged, data may be read continuously at high speed by a short cycle operation using a column address only. Practically, a CPU as a central data processor and a peripheral data processor (for example, a DMA controller) usually continue to access the same page, respectively. Further, Intel Corporation's DRAM Controller 82C08 is one of the known memory controllers for feeding to a memory device a row address RA and a column address CA, in a multiplexed manner.
As explained above, a conventional memory device has been configured so that it only holds row data for one page from the memory cell array 1, in the sense and latch circuit 4. Because of this configuration, if two data processors, for example, alternately access different pages in the memory device, a long cycle operation giving a row address RA and a column address CA is required for every memory access. As the frequency of long cycle operations becomes higher, the advantage of the page mode operation, or quick access may not be achieved. In other words, the average access time becomes longer, and the processing efficiency of a data processing system that employs a memory device of this type drops. In addition, the frequency of operation of the sense amplifiers in the sense and latch circuit 4 increases, which leads to the increase of power consumption in the memory device.
It is therefore an object of the present invention to provide a memory device capable of carrying out a short cycle operation even if different pages are alternately accessed by a plurality of data processors. It is another object of the invention to improve the process efficiency of a data processing system with a configuration in which plurality of data processors access a common memory device.